It also signifies Synplicity’s ongoing commitment to supporting the advancing requirement of FPGA devices,” said Hitesh Patel, director of Software Product Marketing at Xilinx. “The new Synplify Premier product highlights the ongoing benefits of the strong relationship between Xilinx and Synplicity and their work in the Ultra High-Density Task Force. This is the only physical synthesis solution that creates detailed placement for all logic which is then passed on to the vendor tool for final routing. Unlike other solutions, Synplicity’s patented, and award-winning graph-based physical synthesis technology merges logic optimization, placement and routing estimates into a single process which is used alongside a highly accurate interconnect timing graph (database) to help ensure a design’s critical paths use the fastest available routing resources in the target device. Actual testing on customer designs has shown that graph-based physical synthesis provides timing correlation within 10 percent of final post-route timing on over 90 percent of designs resulting in fewer design iterations, less time to completion, and logical and physical optimizations on the actual critical paths of the design. Synplicity’s graph-based physical synthesis is the only product on the market that performs final detailed placement of logic during optimization, and therefore, is the only tool that successfully addresses timing closure. The only proven way to get this timing correlation is to perform detailed placement and routing during logic optimization and also to have access to FPGA-specific routing information (routing graph a.k.a. In order to fully address timing closure, designers must have highly accurate timing correlation between what a tool estimates and the final, actual timing. Port declarations for multiple dimensions.Arrays as arguments to functions, tasks and modules.
New SystemVerilog features in release 9.0 include: These features allow designers to avoid handwriting RTL or using technology dependent memory instantiations for these functions.Īdditionally, Synplicity continues to extend its support for the SystemVerilog language.
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Designers supply parameters to indicate the size and type of RAM or FIFO and the IP generator wizard automatically creates technology independent RTL ready for synthesis into an FPGA. For example, Synplicity has expanded its SynCore IP generator to support FIFOs in addition to RAMs. With the release of Synplify Premier 9.0, Synplicity offers additional features for improved productivity.
The Synplify Premier solution is also a platform for implementation and debug of ASIC and SoC prototypes using a single FPGA. The Synplify Premier Platform is a complete environment offering a range of features including RTL analysis, source-level debug, HDL analysis, advanced floorplanning, physical analysis, module generators and optimizations for DSP design. Synplicity continuously works to expand the breadth of its synthesis technology to provide the most robust platform for FPGA implementation and design.
We are excited to offer graph-based physical synthesis to Virtex-5 designers through Synplify Premier and to Stratix-III designers through our Beta Program.” We worked very closely with our FPGA partners to ensure that Synplify Premier 9.0 supports the intricate architectural elements of these advanced 65-nanometer devices. In addition to providing an optimal solution for timing closure, Synplify Premier 9.0 provides several algorithmic QoR enhancements and productivity boosting features such as a new user interface, additional SystemVerilog constructs and a new module generation capability.Īndy Haines, senior vice president of marketing at Synplicity notes, “The Synplify Premier Platform is a comprehensive environment for FPGA design comprising a variety of tools and technologies that provide improvement in analysis, DSP implementation, debug and productivity needed to successfully complete today’s high-density designs. Once the designer is happy with the results, placement from the Synplify Premier software is passed to place and route to ensure deterministic results and thus the fastest timing closure. Ke other solutions, Synplify Premier 9.0 gives users the most accurate timing information and insight into debug performance-related issues immediately following synthesis.ĭesigners won’t have to go through the hours of place and route, typical in traditional flows, to get detailed timing information.
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